Implementation Technology of Video Processing Engines – Traditions and Trends
Prof. Takao Onoye,
Osaka University, Japan
Wednesday, September 6, 2017
16:00-17:00 at Auditorium
For more than two decades, video processing schemes including video coding and computer vision have taken very important roles in consumer and Internet applications. While video processing schemes enhanced by using sophisticated signal processing algorithms, media processing engines have also improved in terms of processing capability as well as size and power consumption owing to the rapid progress of semiconductor fabrication technology. Nowadays, here exist very compact implementations of high-quality video processing engines applicable for embedded systems. In this talk, growth of media processing engines will be reviewed as well as introducing state-of-the-art ones.
Takao Onoye received B.E. and M.E. degrees in Electronic Engineering, and Dr.Eng. degree in Information Systems Engineering all from Osaka University, Japan, in 1991, 1993 and 1997, respectively. He has worked as a faculty member of Osaka University and Kyoto University for more than 20 years. He is presently a professor and dean of Graduate School of Information Science and Technology, Osaka University. He has also taken various volunteer positions in academic societies, such as IEEE CAS Society board of governors, IEEE Region 10 Treasurer, IEEE Region 10 Vice Chair for Technical Activities, and Editor-in-chief of IEICE Trans. Fundamentals (Japanese edition).
Prof. Yoshikazu Miyanaga,
Hokkaido University, Japan
Thursday, September 7, 2017
16:00-17:00 at Auditorium
This topic introduces the design of a communication robot with a speech recognition system. For the valuable system as a communication robot, the high performance of a strong noisy robust speech recognition would be implemented. Although the dialog mechanism as human communications is one of interesting features into a robot, the command-based communications to a robot may be much more important. When we consider the development of a command-based automatic speech recognition (ASR) system, we can design a strong robust ASR against various noise circumstances.
In this presentation, new advanced speech analysis techniques named time varying speech features have been introduced. In order to develop the robustness under low SNR, Dynamic Range Adjustment (DRA) and Modulation Spectrum Control (MSC) have been proposed for the obtained time-varying speech features and they focus on the speech feature adjustment with an important speech components. DRA normalizes dynamic ranges and MSC eliminates the noise corruption of speech feature parameters.
Even if these proposed algorithms are applied to noisy speech, it is difficult to recognize several similar pronunciation phrases. Discrimination of similar pronunciation phrases is more difﬁcult than that of normal phrases under low SNR circumstances. In this topic, we propose the use of fast Fourier transform (FFT) based mel-frequency cepstral coefﬁcients (MFCC) and time-varying linear predictive coding (tvLPC) based MFCC. Due to the presence of intra-frame variations in tvLPC, it is expected that this approach will improve speech recognition. Evaluation results demonstrate that the proposed approach achieves better speech recognition performance at low SNR conditions.
He received the B.S., M.S., and Dr. Eng. degrees from Hokkaido University, Sapporo, Japan, in 1979, 1981, and 1986, respectively. Since 1983 he has been with Hokkaido University. He is now Dean and Professor, Graduate School of Information Science and Technology, Hokkaido University. From 1984 to 1985, he was a visiting researcher at Department of Computer Science, University of Illinois, USA.
His research interests are in the areas of speech signal processing, wireless communication signal processing and low-power consumption VLSI system design. He has published 3 books, over 150 Transaction/Journal papers, and around 300 International Conference/Symposium/Workshop papers.
Dr. Miyanaga served as an editor-in-chief of IEICE ESS (2016-present). He was an associate editor of IEEE CAS Society Transaction on Circuits and Systems II (2012-2014), and he is also an editor-in-chief of Journal of Signal Processing, RISP Japan (2014-present).
He was a delegate of IEICE, Engineering Sciences Society Steering Committee, i.e., IEICE ESS Officers from 2004 to 2006. He was a chair of Technical Group on Smart Info-Media System, IEICE (IEICE TG-SIS) during the same period and now a member of the advisory committee, IEICE TG-SIS. He was the President, IEICE Engineering Science (ES) Society (2015-2016). He is Fellow member of IEICE.
He served as a member in the board of directors, IEEE Japan Council as a chair of student activity committee from 2002 to 2004. He was a chair of IEEE Circuits and Systems Society, Technical Committee on Digital Signal Processing (IEEE CASS DSP TC) (2006-2008). He was a distinguished lecture (DL) of IEEE CAS Society (2010-2011) and he was a Board of Governor (BoG) of IEEE CAS Society (2011-2013). He is now a chair of IEEE Sapporo Section (2017-present).
He has been serving as a member of international advisory committee, IEEE ISPACS (2005-present), and IEEE ISCIT (2006-present). He was an honorary chair and general chair/co-chairs of international symposiums/workshops, i.e., ISCIT 2005, NSIP 2005, ISCIT 2006, SISB 2007, ISPACS 2008, ISMAC 2009, ISMAC2010, APSIPA ASC 2009, IEICE ITC-CSCC 2011, APSIPA ASC 2011, IEEE ISCIT 2012, ISMAC 2011, ISPACS2011, ISCIT2015, ISCIT2016, ISPACS2016, ISCIT2017, ISCAS2019 and so on.